Electronic digital differential analyzer



May 22, 1962 F. G. STEELE Filed Feb. 10, 1956 7 Sheets-Sheet 1 '-/0 i 2 M/Mese i a z L l 2 ya x I l y m/Maze I y I l L l /-7 .1.

F I I i dz=*/ -ua/ 1 I /0 g z w I Avzeeem 702 556 7704/ 5 J L l w fl n I i I i v I I a i Z aaz I a I -4! I Q. T I /0- d! i :L/NTEGEA 70 2 Sec 7704/ 1 f J "u INVENTOR.

Alas 0 6. 57.5545 F7 2. BY

Arrae/vav May 22, 1962 F. G. STEELE 7 Sheets-Sheet 2 flu c A I FLIP FLIP FLIP 54 FLIP FLIP 7' FLUP FLOP FLOP FLOP FLOP ZA 2; i l a r C] C V M M sczcsa'sazaA A 4 L's/412M Q 5;; FLIP FLOP 2Q 51 I 1:: a GA T/A/G 2; M 21 FLOP A TQ/X I 1 FLIP I FLOP -z 7 z I J, Hwmr 5p FZP 2 F'LOP V p //vpurz' p l I 5/ 244 56025 521 aur or/ 007 /17 2 (9.55 6 52 {"164 ON Pam/5e 645w i 5 E6. 744 Zeeo 04/6 5 466 Z'a'rep foMwra-smrsm -avcz l l I 55 INVENTOR.

A [Zora 6, 575545 Arrae/vy May 22, 1962 F. e. STEELE 3,035,763

ELECTRONIC DIGITAL DIFFERENTIAL ANALYZER Filed Feb. 10, 1956 '7 Sheets-Sheet 4 Smer if J] I ski 645572127 INVENTOR. #Zoxo 6. 57-5545 Arrae/wsy May 22, 1962 F. G. STEELE ELECTRONIC DIGITAL DIFFERENTIAL ANALYZER '7 Sheets-Sheet 5 Filed Feb 10, 1956 INVENTOR.

A/sgr 11. 54 4 7- 557' M GA TVA/6 A/5rwae4 Z550 M GA T/NG #5720025 May 22, 1962 F. G. STEELE ELECTRONIC DIGITAL DIFFERENTIAL ANALYZER 7 Sheets-Sheet 6 Filed Feb. 10, 1956 May 22, 1962 F. G. STEELE ELECTRONIC DIGITAL DIFFERENTIAL ANALYZER Filed Feb. 10, 1956 '7 Sheets-Sheet 7 INVENTOR. A20 Y0 6. 575545 United States Patent Ofitice 3,035,768 Patented May 22, 1962 3,035,768 ELECTRONIC DIGITAL DIFFERENTIAL ANALYZER Floyd George Steele, La Jolla, Calif., assignor to Digital Control Systems, Inc., La Jolla, Calif. Filed Feb. 10, 1956, Ser. No. 564,683 51 Claims. (Cl. 235152) The present invention relates to electronic digital computers and more particularly to an electronic digital differential analyzer incorporating unique concepts which occasion greatly reduced equipment complexity and considerable gains in functional performance.

A diflerential analyzer is usually considered conceptually to be made up of a number of integrators with associated facilities for readily interconnecting these integrators for the solution of differential equations. Since all physical problems and most purely mathematical problems can be reduced to difierential equation form, the differential analyzer in its various embodiments (mechanical, electronic analogue, and electronic digital) has become an exceedingly powerful and important tool for the analysis of such problems.

An integrator for purposes of illustration may be considered to be a device in which an initial value y is stored and which responds to input rates dy and dx to produce an output rate dz which is related to the input rates by the equation:

where k is an arbitrary scaling constant which is introduced in the operation In a ditferential analyzer, the dz output rates produced by each integrator are available to other integrators for use thereby as dx and dy input rates. Interconnection between integrators is established in this manner, i.e. by selectively connecting the dz output of each integrator to the dx and/or dy input of the same or other integrators. Through suitable interconnection of integrators, as herebefore mentioned, problem solutions are developed by an analyzer.

In mechanical differential analyzers of the well known Bush-Caldwell type, dx and dy inputs and dz outputs of an integrator are provided in the form of shaft rotations and the y value y -t-fdy is stored within the integrator as the inear displacement of a shaft. Interconnection between integrators is therefore accomplished by selectively coupling the (dz) output shaft of each integrator to the (dx and/ or dy) input shafts of that or other integrators. In an electronic analogue differential analyzer the y value of an integrator is held as a voltage stored on a capacitor and dy inputs and dz outputs of the integrator are provided as input and output voltages. Commonly an integrator of an electronic analogue analyzer cannot accept a variable dx input but is constrained to integrate with respect to time t so that dx=dt for all integrators. This places great limitations on the use of electronic analogue differential analyzers. Interconnection of integrators in such an analyzer is accomplished by physically connecting conductive wires between the dz output of each integrator and the inputs to which the dz signal is to be applied.

In the electronic digital differential analyzer the y value of an integrator is held stored in digital form as a socalled Y number. The dx and dy input rates and dz output rates are provided as pulse coded signal trains. In a number of digital differential analyzers each signal of such a signal train has a significance of +1 or 1 scaled to the weight of the lowest order digit of the Y number. In this representation, a positive rate is indicated by an excess of +1 valued signals in the signal train which represents the rate and a negative rate is indicated by an excess of 1 valued signals while a zero rate is indicated by alternate +1 and 1 valued signals in the signal train. (It should be noted that other forms of rate representation have also been used, as for example the so-called ternary representation in which corresponding signals in two pulse coded signal trains are utilized to represent the values +1, 0, or 1.) Increase or decrease of the y value of an integrator in accordance with the equation y y +fdy is accomplished by adding or subtracting 1 respectively from the Y number for each +1 or 1 valued dy input signal received.

Production of dz output signals by an integrator in accordance with the equation dz=kydx is accomplished through use of a so-called R number which is associated with the Y number. For each +1 or -1 valued dx signal received the Y number is accordingly added to or subtracted from the R number. In this way the Y number is effectively added to the R number at the rate dx. Eventually the R number will overflow-that is exceed predetermined limits assigned to the R number-and the rate at which such overflows occur is taken at the output rate dz. Each time the R number overflows in response to addition or subtraction of the Y number the carry digit produced in the formation of the highest order digit of the R number is treated as a +1 valued dz output signal; while on the other hand each time the R number does not overflow in response to such addition or subtraction the carry digit produced is treated as a l valued dz output signal, the train of successive dz signals thus provided forming the dz output rate.

In view of what has already been explained, it is clear that in a digital dilferential analyzer an individual integrator need not necessarily exist as a separate and distinct physical entity but instead may comprise a stored Y number and an associated stored R number and apparatus for performing the following operations on these numbers in response to applied dz signals: utilizing selected dz signals as dx and dy inputs; decreasing or increasing the Y number in accordance with each dy input; adding or subtracting the Y number from the R number in accordance with the dx input; and producing dz output signals in accordance with the resultant overflows of the R number. In the same manner a plurality of integrators may be provided by storing a plurality of pairs of Y and R numbers and operating serially upon each pair of Y and R numbers, the apparatus for performing these operations thus being time shared so that it successively services each pair of Y and R numbers.

One early multiple integrator electronic digital differential analyzer of the described type to appear commercially was the Maddida machine, which utilized a rotating magnetic drum for the storage of a plurality of pairs of Y and R numbers thereon. The Maddida machine contained nearly tube envelopes (excluding power supply) and almost 1000 crystal diodes in its circuitry for operating upon these pairs of Y and R numbers. Even considering its electronic complexity, the Maddida offered great advantages over the prior art mechanical and electronic analogue analyzers.

Other digital analyzers appearing commercially since the Maddida have tended to develop in the direction of ever increasing electronic complexity partly because of their operation in the binar coded decimal number system rather than the binary number system and partly because of the engrafting of additional features upon the original Maddida design without adequate revision of the basic machine concepts to fully coordinate and integrate these additional features into a new machine design.

The present inventor has long felt that great effort should be directed at simplification rather than elaboration of the electronic complexity of electronic digital differential analyzers, hereinafter referred to as DDAs.

In accordance with this object, the present inventor conceived a novel DDA hereinafter called DDA 780 which is fully disclosed and explained in U.S. patent application 388,780, entitled Electronic Digital Differential Analyzer, filed October 28, 1953. As disclosed, DDA 780 holds twenty pairs of Y and R numbers stored in interplexed form on a single recirculating channel (called the long channel) of a magnetic drum. The successive pairs of Y and R numbers each with associated decode (dz selection) indicia are stored in respectively successive sections (integrator sections) of the long channel. The drum includes an additional recirculation channel (the short channel) in which are continuously stored the most recent dz output signals produced by the twenty integrator sections. The length of the short channel corresponds to one-half of a single integrator section so that the contents of the short channel recirculate twice during each passage of an integrator section.

Because of this operation all of the dz signals contained in the short channel are serially presented during each passage of an integrator section. So-called dx and dy decode marks are filled (selectively recorded) in the first half (decode portion) of each integrator section. These decode marks as they appear have the efiect of selecting corresponding dz signals from the short channel for introduction to the integrator section as dx and dy inputs which will control operations to be performed upon the pair of interplexed Y and R numbers stored in the second half (integrate portion) of the integrator section. In response to such dx and dy inputs new Y and R numbers are formed and rewritten in the integrator section in the spaces formerly occupied by the old Y and R numbers, the carry signal resulting from the formation of the highest order digit of the new R number being introduced into the short channel as the most recent dz output sigaal of the integrator section.

To simplify in DDA 780 the introduction of such a dz output signal into its appropriate position in the short channel, a so-called m mark is initially filled into and maintained in the first cell of the short channel and the dz signals in the short channel are regularly precessed with respect to the m mark so that at each passage of an integrator section the appropriate position for the dz output signal produced by the integrator section is immediately behind the m mark. As a result of this precession operation every other appearance of the m mark indicates that the then produced dz output signal should be recorded immediately behind the 111 mark. The m mar-k is also utilized in conjunction with a two stage programming counter to identify the decode and integrate portions of each integrator section. The m mark of course appears twice during the passage of each integrator section, its first appearance indicating the beginning of the decode portion and its second appearance indicating the beginning of the integrate portion of the integrator section.

One feature of the prior art DDA 780 is that coding facilities are provided for each integrator section for selecting a plurality of dz signals for introduction to the integrator section as dy inputs thereto, these signals being accumulated and summed in a four stage Edy flip-flop counter, the sum (Edy) thus formed in the counter being serially added to the Y number upon its appearance. As a result of this feature each integrator section can be interconnected on its dy input with a plurality of other integrator sections. The four stage Edy counter can hold the numbers +7 to 7 and therefore each integrator section can receive ay inputs from at most seven other integrator sections unless additional flip-flop stages are provided for the four stage Edy counter.

Although multiple dy inputs to an integrator section could be provided in DDA 780 in the described manner, no facilities were provided for summing dx inputs to an integrator section. Ordinarily therefore each integrator section in DDA 780 can receive a dx input from only one other integrator section. Under certain conditions a second dx input can be received from a second integrator section, this second dx input if a 1 value having no effect and if a +1 value having the effect of reversing the sign of the first dx input. Thus in DDA 780 sign reversal of dx inputs may be accomplished by initially filling one integrator section so that it continuously produces +1 dz output signals, these output signals being utilized as second (sign reversing) dx inputs for those integrator sections where sign reversal of the dx input is required. The disadvantage of this method of providing sign reversal is that an entire integrator section has to be devoted to the task of producing uniform +1 valued sign reversal outputs, thus reducing the number of integrators available for problem solution. An additional disadvantage is that there are no facilities for providing sign reversal of dy, an operation which is often desirable.

Even considering its limitations DDA 780 represented a remarkable achievement from the point of view mathematical power and of reduction of electronic complexity. Only thirteen electronic flip-lop units and approximately 300 diode rectifiers were required for the mechanization of DDA 780. Thus the number of components required in DDA 780 was far fewer than the number required in prior art DDAs, resulting in high reliability and great reductions in size and cost.

However the present inventor has now conceived and developed the DDA of the present invention which incorporates a number of outstanding improvements over DDA 789. In the DDA of the present invention the component count has been considerably reduced, there being only ten flip-flop units in the DDA of the present invention as compared with thirteen in DDA 780 and there being approximately thirty percent fewer diodes required for equivalent mechanizations. Moreover in the DDA of the present invention virtually all of the above-described disadvantages of DDA 780 have been corrected and in addition a number of valuable new operating features have been incorporated.

Probably the most significant feature of improvement is that the four stage Edy counter has been largely eliminated, summing of multiple dy input signals being accomplished by an entirely different process which requires only two flip-flops for its mechanization and which is capable of summing an indefinite number of dy inputs (rather than being limited to a maximum of seven inputs) without requiring any additional circuitry.

According to this new process for summing input signals, each integrator section which is to receive multiple d y input signals has stored therein a number which is designated the Edy remainder number, the digits of this remainder number being stored on the memory surface in the same way that other signals of the integrator section are recorded.

At each passage of such an integrator section, all of the multiple dy signals which are to be received by that integrator section are successively added to the remainder number to form a sum, at least the highest order digit of this sum being utilized as the dy input to the integrator ection while the lower digits of the sum are rewritten in the memory (in the same positions within the integrator section) as the new remainder number. Effectively what has been accomplished is that plural dy input signals to an integrator section are now summed and stored in the memory rather than in an external flip-flop counter, at least the highest order digit of each sum being supplied as the dy input to the associated integrator section and remaining igits being stored in the memory to modify later summations. Other unique features of the summation operation will appear at later points in the present specification.

Another important improvement found in the present DDA relates to the sign reversal operation. In the present DDA each integrator section contains a cell in which a so-called sign reversal mark may be filled. If a sign reversal mark is initially placed in the integrator section each dx input received by the section thereafter is automatically reversed in sign upon the appearance of the sign reversal mark. Thus in the present DDA it is no longer necessary to use up an integrator section to accomplish sign reversal of dx inputs, sign reversal now being readily coded into the machine through use of the sign reversal marks.

It will be recalled that in DDA 780 only dy inputs could be summed and only dx inputs could have their sign reversed. In the present DDA it is possible to vary this normal operation so as to sum dx inputs and also to apply sign reversal to dy inputs. This is accomplished by use of a so-called exchange operation. When the exchange operation is utilized in connection with an integrator section, dx and dy inputs to that section are effectively interchanged after their formation so that the signal formed by the summation operation can serve as the dx input and a signal which has previously had its sign reversed can serve as the dy input to the integrator section. A single exchange mar filled into an integrator section orders the performance of the exchange operation for that integrator section.

Another improvement in the present DDA over DDA #780 is the elimination of a flip-flop which in DDA 780 is devoted to holding each dx input throughout the addition of the associated Y and R numbers. It will be recalled that each Y number is to be added to or subtracted from the corresponding R number in accordance with the sign of the associated dx signal. Since the operation required for subtraction of two binary numbers is different from that required for addition, it is necessary to continuously know throughout the operation whether an addition or subtraction is to be performed (i.e. know the sign of dx throughout the operation). However in the present DDA each Y number is stored in so-called difference notation rather than normal binary notation. Because of certain unique features of the difference notation, it has been possible to develop a process for combining the Y and R numbers in which knowledge of a'x is required only at the time that the first or lowest order digit of the new R number is formed. After that time knowledge of dx is no longer required and the flip-flop which held dx may thereafter be utilized for other purposes in combining the Y and R numbers. Moreover the use of difierence notation allows considerable reduction in the number of diode rectifiers required for mechanizing the combining of the Y and R numbers.

Another important advantage of the present DDA is that accuracy of computation has been considerably increased by the incorporation in each integration of socalled round-ofi and trapezoidal corrections whose nature will be later explained. The inclusion of these corrections greatly reduces growth of error in the Y and R numbers caused by the limited length of these numbers and by the integration approximations which are utilized. The corrections are introduced in novel and extremely simplified manner by developing an initial carry digit which is utilized in forming the first digit of the new R number. The introduction of the correction is further simplified by using a relationship which has been discovered to exist between the corrections and the dy signal.

An additional important improvement in the present DDA relates to the novel manner in which the decode and integrate portions of each integrator section are demarked by so-called phase control marks which are filled into every other cell of the short channel; In DDA 780 the beginnings of the decode and integrate portions were indicated by the appearance and reappearance of the m mark. In order to be continuously apprised of the phase of operation (decode or integrate) throughout the passage of an integrator section it was necessary to utilize the m mark at each appearance to change the state of two programming flip-flops to indicate the phase of operation begun, these flip-flops then providing the continuous or prolonged phase control information which is required. In the present DDA however, by providing a plurality of phase control marks distributed throughout the short channel, these marks themselves continuously (since one of them always appears in either the read or write flip-flop of the short channel) provide the required phase control information. On an automatic basis each signal applied to the write flip-flop of the short channel is reversed in value. Thus during one recirculation of the short channel (during passage of the decode portion) all of the phase control marks appearing in the read flipflop have 0 values and during the next recirculation of the short channel (during passage of the integrate portion) have 1 values because of the described reversal of signal. In this manner the phase control marks continuously indicate by their 0 and 1 values whether the DDA is in a decode or integrate phase of operation.

Obvious advantages fiow from use of the phase control marks in this manner. Since an m mark is not filled into the short channel, it is not necessary to have special filling and marking operations for the short channel. Since the described reversal of signals in the short channel is an automatic function of the DDA, initial filling of phase control marks (and also of initial 0 values of dx signals) into the short channel is automatically accomplished whenever the DDA is cleared. In addition much of the logical gating in the DDA, particularly that gating which is associated with the read and write flip-flops of the short channel, is greatly simplified since identification of the decode or integrate phase of operation is already inherent in the contents of these flip-flops. Moreover a l gating which in DDA 780 was associated with the setting of programming flip-flops by the m mark is eliminated in the present DDA.

An additional feature found in the present DDA which is not found in DDA 780 is that input and output facilities are provided for supplying certain of the dz signals to external output units (such as graph plotters) and also for accepting input signals provided by external input units (such as curve followers, other DDAs, or other input de vices). Besides the obvious convenience offered by this feature, it should also be noted that this feature allows the DDA to be linked up with other DDAs to produce exceedingly powerful computing ensembles, and also permits the DDA to be readily incorporated in digital simulation equipment.

Still another improvement which is incorporated in the DDA of the present invention is related to the manner in which signals are Written into the long channel. Each signal appearing in the read flip-flop of the long channel is uniformly transferred to the write flip-flop of the channel either reversed (complemented) or unchanged in value in accordance with the high or low level of a control signal designated X. All entry of signals into the long channel is therefore accomplished by controlling the X signal. Strict adherence to this mode of operation at all times has permitted important and often surprising logical simplifications in the operations performed on the signals of the long channel.

It is therefore an object of the invention to provide a DDA having many fewer components than prior art instruments and yet providing greater mathematical power and facility of coding.

It is another object of the invention to provide a DDA, employing a cyclically operable memory device, which includes equipment for summing multiple inputs to an integrator section without requiring an electronic summation counter external to the memory.

It is an object of the invention to provide a multiple integrator DDA, employing a cyclically operable storage device, which includes apparatus for cyclically summing a plurality of dz signals received by an integrator section storing lower order digits of the sum in the storage device and supplying at least the highest order digits of the sum to the integrator section as an input thereto.

It is another object of the invention to provide, in a cyclically operable magnetic memory DDA, apparatus for serially selecting at each cycle of operation a plurality of dz outputs originated by predetermined integrator sections and serially adding each of these dz signals to a remainder number stored in the magnetic memory, at least the highest order digit of the sum thereby produced being supplied to an associated integrator section as an input thereto while lower digits of the sum are stored in the magnetic memory as a new remainder number.

It is an object of the invention to provide a cyclically operable magnetic memory DDA which includes apparatus for summing a plurality of output signals originated by predetermined integrators, applying at least the highest order digit of the sum to-an associated integrator section, and storing lower order digits of the sum in the magnetic memory.

It is an object of the invention to provide a DDA including apparatus for reversing the sign of a dx or dy input to an integrator section by utilization of an associated sign reversal mark stored in the memory of the DDA.

It is another object of the invention to provide a DDA in which a dx or a'y input received by an integrator section may be uniformly reversed in sign in response to appearance of a predetermined sign reversal mark initially filled into the integrator section.

It is an object of the invention to provide a DDA including circuitry for exchanging or interchanging the normal dx and dy inputs to an integrator section after their formation.

It is another object of the invention to provide a DDA wherein normal dx and dy inputs to an integrator section are exchanged after their formation in response to appearance of a predetermined exchange mark filled into the integrator section.

It is yet another object of the invention to provide a DDA having facilities for summing dz signals to form a normal dy input to an integrator section and further including circuitry for thereafter exchanging the normal dx and dy inputs to produce a ax input representing the summation of the dz signals.

It is still another object of the invention to provide a DDA having circuitry for reversing the sign of a normal dx input to an integrator section and further including means for thereafter exchanging the normal dx and dy inputs to produce a dy input which is reversed in sign.

It is an object of the invention to provide a DDA in which Y numbers are added and subtracted from corresponding R numbers in accordance with the sign of associated dx input signals wherein storage and knowledge of the value of a dx input is only required at the time the first digit of an associated Y number is combined with the first digit of the corresponding R number.

It is another object of the invention to provide a DDA wherein Y numbers are stored in difference form so that additions or subtractions of a Y number from an R number in accordance with a dx input signal are accomplished by identical operations varying only as they aifect the first digits of the Y and R numbers, the dx signal being required only at the time the first digit of the Y number is combined with the first digit of the R number.

It is an object of the invention to provide a DDA wherein trapezoidal and round-off corrections are added to an R number by forming a single carry digit which is utilized in forming the lowest order digit of the new R number.

It is another object of the invention to provide a DDA wherein a correction added to the R number of an integrator section is a single digit equal to dy when dx equals +1 and the reverse of dy when dx equals 1.

It is an object of the invention to provide means for demarking successive equal length portions of a first cyclically operable storage channel by providin a plurality of like valued information signals stored in a recirculation channel whose length is equal to one of said portions and which includes means for automatically reversing the value of each signal as it is rewritten therein, whereby the information signals appearing have alternate values at each recirculation of the short channel and thereby demark successive equal length portions of the storage channel.

It is another object of the invention to provide a DDA wherein successive decode and integrate portions of a long recirculation channel are identified by phase control marks filled into a short recirculation channel whose length is equal to one of said portions, each mark being reversed in value as it is rewritten in the short channel so that the marks appearing have alternate values at each recirculation of the short channel to thereby identify the successive decode and integrate portions.

It is an object of the invention to provide apparatus for operating upon bivalued signals stored in a recirculating channel by uniformly transferring each signal from a read point to a write point of the channel either unchanged or reversed in value in accordance with the value of an applied control signal.

It is another object of the invention to provide means for introducing successive input signal information into an information signal recirculating channel by transferring each information signal between read and write points of the channel either reversed or unchanged in value in accordance with the value of a control signal, the control signal having one value whenever an input signal has the same value as a simultaneously appearing information signal and having its other value whenever an input signal value is different from the value of a simultaneously appearing information signal.

The novel features which are believed to be characteristic of the invention both as to its organization and method of operation, together with further objects and advantages thereof, will be better understood from the following description considered in connection with the accompanying drawings in which a preferred embodiment of the invention is illustrated by way of example. It is to be expressly understood, however, that the drawings are for the purpose of illustration and description only, and are not intended as a definition of the limits of the invention.

FIG. 1 is a block diagram illustrating a functional representation of an integrator section;

FIG. 2 is aschematic diagram illustrating the interconnection of two functionally represented integrator sections for the solution of a predetermined differential equation;

FIG. 3 is a schematic diagram in partly block form illustrating a magnetic drum DDA which is a preferred embodiment of the present invention;

FIG. 4 is a functional diagram illustrating for purposes of example the contents of one integrator section of the DDA and also illustrating on a common time scale the contents of the short channel during passage of the integrator section;

FIG. 5 is a diagram illustrating the waveform of one flip-flop output signal as it would appear during passage of the integrator section shown in FIG. 4;

FIGS. 6a and 6b are circuit diagrams illustrating the construction of four gating networks and a gating circuit which are included within a gating matrix of the DDA;

FIGS. 7a through 7e are circuit diagrams illustrating seven switches which are utilized in the DDA and also presenting various Waveforms which are illustrative of the operation performed by these switches.

Mathematical Concepts In order to fully understand the manner in which the DDA of the present invention is mechanized, it is desirable to have some familiarity with the mathematical concepts which underlie the use of the DDA. One of the best ways of developing these concepts is to consider briefly some of the operations performed by a coder or mathematician in formulating and coding a problem for solution by the DDA.

Basically to solve a problem with the DDA what is required of a coder is that he discover how integrator sections of the DDA should be interconnected in order to develop a problem solution and also to specify initial values for the Y numbers which are contained in those integrators. Once these interconnections and initial Values have been found, they are readily entered into the DDA. interconnections between integrator sections are established by initially filling appropriate dx and dy decode marks into the integrator sections being utilized and initial values of the various Y numbers are entered by filling the digits of these numbers into spaces reserved therefor in the various integrator sections.

In accomplishing his duties a coder does not require exact knowledge as to how integrator sections are disposed and mechanized but instead can make use of diagrammatic or functional representations of the integrator sections, which are sufiicient for his purposes. Such a functional representation of an integrator section, integrator diagram 10, is shown in FIG. 1 and is seen to comprise a depiction of a Y number (which represents a y value), an associated R number, dx and dy inputs for controlling operations upon these numbers, and a dz output which represents the product ydx. It is, of course, understood that the Y number is increased or decreased by the +1 or 1 values of each dy input and that the Y number is added to or subtracted (by adding its complement) from the R number in accordance with the +1 or 1 value of each dx input signal, the carry digits originating from the highest order digit of the R number serving as the dz output signals.

The R and Y numbers are assumed in the following discussion to be expressed in binary form, and are assumed to each have the same number of digits. (Actually for purposes of equipment simplification, the Y number in the present DDA is stored in so-called difference form which is closely related to the binary form.) The Y number will be assumed to have 11 digits to the right of the binal point and one digit (a so called sign digit) to the left of the binal point so that the Y number can express the numbers lying between zero (0.0000 and almost two (1.1111 Since theRnumber has the same number of digits as the Y number, it has n+1 digits and for convenience the highest order digit of the R number is designated as R As stated before a Y number of an integrator section represents a y Value which is held stored in the integrator section. The relationship that exists between a Y numer and the y value it represents is that:

where y is allowed to have any value lying between +1 and 1. Thus if a coder decides that an initial y value of /z is to be filled into an integrator section, he forms the Y number 1 /2 (in binary 1.10000 and, after converting this binary Y number to difference form, fills it into the integrator section. The mathematical basis for the described representation of y values by corresponding Y numbers will not be presented here since it has been described in detail in the prior art literature relating to DDAs (see article entitled, The Decimal Digital Diiferential Analyzer, by Mendelssohn, in Aero Engineering Review, February 1954) and is also specifically described in the above-mentioned copending US. patent application Serial No. 388,780.

'1 he manner in which required interconnections of integrator sections are found for solution of a specified differential equation is illustrated in FIG. 2, wherein is shown a diagrammatic set-up for the solution of the following difierential equation.

A a preliminary step, this equation is rewritten as a difference equation of the form:

To solve this equation, it is first assumed that the rate is available as an input to an integrator section. Then by means of successive integrations the rates (-du) and (udt) are developed. These rates are then summed to form a resultant rate (-du)+(-udt). Since this resultant rate is equal to it is utilized as such and [thereby supplies the originally assumed input rate du d As shown diagrammatically in FIG. 2, only two integrator sections (integrator sections 1 and 5 for example) are required for the solution of this problem. As explained hereinabove and shown in FIG. 2, the rate du d is assumed available and is applied as a dy input to integrator section 1 so that the quantity is accumulated and represented by the Y number of integrator section 1.

To form the first required output rate du, the rate dt must be applied as the dx input to integrator section 1. It will be appreciated that the rate dt is the rate of the independent variable of Equation 2 and may therefore be assigned any arbitrary value. For purposes of coding simplification it is assigned the Value +1, for the reason that in the present DDA a +1 rate is always automatically available to the dx input of each integrator section if no other dx inputs are coded therein. The required output rate (du) is therefore obtained from integrator section 1 by utilizing this automatically available +1 rate as the rate di and reversing its sign (as indicated by the symbol 6) to form a dt rate which is applied as the dx input to the integrator section.

To form the second required rate udt) another integrator section (integrator section 5), is utilized. The rate du is applied as a dy input to integrator section 5 so that the quantity u is accumulated therein. Since the required output rate equals (--udt) the rate dt must be applied as a dx input to integrator section 5. Thus as shown in FIG. 2 the automatically available +1 rate is again utilized as the rate dt and is applied to the dx input of integrator section 5. The output rate produced by integrator section 5 is accordingly zcdt. (If a dt rate other than +1 were desired, it would be supplied, by appropriate coding, from other integrator sections or could even be supplied from an external source such as a curve follower.)

The only step remaining is to sum the two rates du and udt to form the resultant rate (-du)+(-udt) and provide this resultant rate as the dy input rate du a) of integrator section 1. This summation as indicated in FIG. 2 is automatically accomplished within integrator section 1.

A preliminary coding diagram has therefore been completed which serves to indicate to the coder what integrator interconnection and initial conditions are required for the solution of equations. For example from FIG. 2, it is clear that for the solution of this problem appropriate initial values of I and -l[ must be filled into the memory as the Y numbers of integrator sections 1 and respectively. In integrator section 1 a sign reversal mark must be filled and also two dy decode marks in appropriate positions to select the dz outputs of integrator sections 1 and 5 respectively. As explained no dx decode mark need be filled in the integrator section since the +1 rate is then automatically available. In the same manner referring to integrator section 5 it is clear that a dy decode mark must be filled therein in an appropriate position to select the dz output of integrator section 1. Once again a dx decode mark is not required since the automatically available +1 rate is utilized.

In further coding steps the question of appropriate scaling relationship would be considered. Scaling of a problem is largely controlled by varying the eflfective lengths of the Y and R numbers and also through choice of initial values of Y numbers. However the scaling operations will not be discussed here since these problems are mathematically complex in nature and familiarity with them is not required for understanding of machine operation.

Generalized Description of the DDA Referring now to FIG. 3, there is shown a magnetic drum DDA according to the present invention which is seen to comprise as its basic components a rotatable magnetic drum 3! with associated magnetic transducers and read-write circuitry for reading and writing magnetic signals on the surface of the drum; a plurality of flip-flops designated A, B, C, L, M, I, P, Q, I and T respectively; a gating matrix 31 which receives output signals from the flip-iops and applies resultant input signals to the flipfiops; and a control panel 32, including a plurality of control switches which are utilized for generating electrical signals. These signals, called switch signals are also applied to gating matrix 31 to initiate and control the various operations of the DDA.

As shown in FIG. 3, drum 30 has three magnetizable tracks or bands 34a, 34b and 34c established about its periphery.

In track 34a, a timing signal waveform or socalled clock pulse waveform is permanently recorded, this waveform comprising a large plurality of evenly spaced timing signals recorded about the periphery of the drum as successively adjacent regions or cells of the drum surface which are alternately magnetized in opposite directions of polarization. Upon rotation of drum 30 each passage of a recorded timing signal beneath a magnetic recording or transducer read head 35, which is positioned adjacent track 34a, causes the head to produce a corresponding electrical signal, these electrical signals being a lied to a wave she in circuit or clock ulse enerator 36 which converts the signals to an output train of sharp electrical clock pulses Cl. Each appearance of a clock pulse Cl indicates that one of the magnetized timing cells on track 34a is passing beneath head 35. The clock pulses Cl are utilized to synchronize almost all of the operations of the computer, transitions in the electronic 1 or 0 states of the flip-flop circuits being made only upon the appearance of a clock pulse signal, and recording in magnetic form of bivalued l or 0 signals upon tracks 3% and 340 being synchronized with the clock pulses in such a manner that these tracks are effectively divided into discrete cells, corresponding to the timing track cells, in which a single bivalued signal may be recorded as one of two alternate directions of magnetic polarization.

In track 34b, a recirculating binary information channel (called the short channel) having a storage capacity of forty bivalued signals is maintained over that segment of the track, designated segment 38, lying between a write head 39 and a read head 40 which are positioned adjacent track 34b. In track 34c a second recirculating channel, designated the long channel havi2 ing a storage capacity of 1600 bits, is maintained over that segment of track 340, designated segment 42, lying between a write head 44 and a read head 45 which are positioned adjacent track 340. Tracks 34b and 34c are also provided with erase heads 41b and 410, respectively, for erasing the signals stored in the channels after such signals have passed read heads 40 and 45.

A recirculating binary information channel is a type of storage device, well known to those skilled in the art, in which bivalued signals recorded at a write point are transported after a predetermined delay to a read point, each signal received at the read point being reapplied to the write point, so that in operation signals recorded at the write point circulate and recirculate through the information loop thus established.

For the short channel of the present invention, the path of information flow for signals recorded on track 2541) by write head 39 is briefly as follows: 1 and 0 signals so recorded pass from write head 39 to read head 46 and thence pass by means of a read circuit 46 to flip-flop A where they appear as corresponding electrical l or 0 states of flip-flop A. From flip-flop A the signals are ordinarily transferred, through operation of gating matrix 31, directly to fli -flop C. In the transfer from flip-flop A to flip-flop C the signals are reversed in value, so that l and 0 signals appearing in flip-flop A appear next in flip-flop C as 0 and 1 signals respectively. Flip flop C in turn controls a write circuit 47 which is coupled to write head 39, and in this manner flipi'lop C is effective for writing or recording beneath write head 39 the signals transferred to the flip-flop, thereby completing a loop for recirculation of information signals. In certain operations of the computer, flip-flop B is inserted within this recirculation loop between flip-flops A and C, so that signals pass from flip-flop A to flip-flop B before being transferred, reversed in value, to fiip-fiop C.

As stated hereinbefore the above-described short channel has a storage capacity of 40 bivalued signals or bits, the total time required for a bit to traverse the recirculation loop therefore being equal to 40 timing intervals as demarked by clock pulses Cl. In the particular embodiment of the invention shown in FIG. 3 the spacing between write head 39 and read head 4% corresponds very nearly to 40 cell spaces, each signal therefore being delayed substantially, the entire 40 timing intervals in passing from write head 39 to read head 40, negligible additional delay encountered by the signal as it traverses the remainder of the short channel recirculation loop through flip-flops A and C. Figuratively speaking flip-flops A and C act as windows through which the respective contents of the magnetic cells passing beneath read head 41 and write head 39 are simultaneously displayed in electrical form.

In the same manner, referring now to the long channel which has a storage capacity of 1600 hits, the length of segment 42 extending from Write head 44 to read head 45 is substantially 1600 cells. The recirculation loop for a single passing from write head 44- to read head 4-5 is completed through a read circuit 48, flip-flop L, flip-flop M and finally through a write circuit 49 back to Write head 44-. Each signal passing from Write head 44 to read head 45 is thus transferred by means of read circuit 48 to flip-flop L and thence through operation of gating matrix 3?. to flip-flop M which applies the signal through write circuit 49 to write head 44 to thereby complete the recirculation loop. In each transfer of a bivalued signal from flip-flop L to flip-flop M, the signal is either transferred unchanged or complemented in value in accordance with the values of signals applied to gating matrix 31 by the computer flip-flops. In certain of the operations of the computer known as the fill operations flip-flop B is utilized to control gating matrix 31 so that signals transferred between flip-flops L and M are eifectively passed from L to B and thence to M.

In operation of the specific embodiment hereinbelow described of the DDA of the present invention, the 1600 cells of the long channel are divided into twenty equal integrator sections, each integrator section having twice the length of the short channel and therefore comprising eighty consecutive cells of the long channel. In each individual integrator section are stored all of the signals relating to the operation of a single integrator. The nature of these stored signals will be explained in more detail hereinbelow. However it will be understood at this time that each integrator section includes signals representing a pair of associated Y and R numbers and also so called dx decode signals and dy decode signals which in operation control the introduction of dz information into the integrator sections. The first forty cells, denoted the decode portion, of each integrator section are utilized for the storage of the dx and dy decode signals; while the remaining forty cells, denoted the integrate portion, of each integrator section are utilized for the storage of the signals representing the associated pair of Y and R numbers. Thus the decode and integrate portions each have the same length (forty cells) as the short channel.

Within the forty cells of the short channel are recorded bivalued signals representing the dz overflows arising from the twenty integrator sections. Since the short channel has the same length as a decode portion in the long channel, all of the dz representing signals in the short channel will pass beneath read head 40 during the time required for a decode portion to pass in the long channel beneath read head 45. The short channel will then, accomplish another turn (another complete circulation of its stored signals) as the succeeding integrate portion passes beneath the read head. Thus the short channel turns twice during the passage of an integrator section, turning once for the passage of a decode portion and turning again for the passage of the succeeding integrate portion.

To assist in understanding this operation, it is helpful to refer again to FIG. 3 and to assume for purposes of example that an integrator section is just beginning to travel past read head 45, the first cell of the integrator section then lying beneath read head 45 and the signal contained therein simultaneously appearing in flip-flop L. The decode portion of the integrator section will then extend over a segment 50 of track 340 corresponding in length to segment 38 of the short channel; while the succeeding integrate portion would extend over an immediately succeeding equal length segment 51 of track 340.

Referring now to FIG. 4 there is shown a diagram which symbolically represents the contents of segments 38, 5t) and 51 for that situation in which the seventh integrator section of the twenty integrator sections is just beginning to pass beneath read head 45. Since signals stored in the serially appearing cells of the short and long channels will be serially available in the same order in flip-flops A and L respectively, the diagram of FIG. 4 may also be thought of as symbolically displaying on a right-to-left scale, the successive signals which will be contained in flip-flops A and L during the eighty timing intervals required for the passage of the eighty cells of the integrator section beneath read head 45.

In accordance with this time datum there are also shown in H6. 4 one voltage waveform representing the clock pulses Cl which demark the successive timing intervals and a pair of waveforms representing output signals produced by flip-flop T in response to the application thereto of the successive clock pulses Cl. These output signals produced by flip-flop T are designated signal T and signal T respectively. As illustrated in FIG. 3, each clock pulse Cl is simultaneously applied to both input conductors (designated ST and ZT respectively) of flip-flop T, this having the effect it will be understood of reversing the electrical state of flip-flop T upon each appearance of a clock pulse Cl. Thus flip-flop T has alternate 0 and "1 electrical states during successive timing intervals. These alternating electrical states of flip-flop T are manifested externally by the voltage levels of the complementary output signals T and T produced by flip-flop T, signal T having a high voltage level whenever flip-flop T is in its 1 state and a low voltage level when flip-flop T is in its 0 state, while on the other hand complementary signal T has respectively corresponding low and high voltage levels.

A similar nomenclature will be adopted for designating I the pairs of complementary output signals produced respectively by the other flip-flops in the DDA, flip-flops A, B and C for example each producing a corresponding pair of complementary output signals A and A, B and B, C and C respectively, each pair of output signals indicating the state of the associated flip-flop in the described manner. For purposes of clarity, all conductors will be normally designated in terms of the signals applied over the conductors, the conductor for example over which signal T is applied being referred to as conductor T. Moreover it will be understood that each flip-flop has a pair of set and zero input conductors designated the S and Z input conductors respectively and further designated by an alphabetical postscript corresponding to the alphabetical designation of the flip-flop. For example ST and ZT, SA and ZA, SB and ZB are the pairs of input conductors associated with flip-flops T, A and B respectively and the input signals applied over these conductors are correspondingly designated as the signals ST and ZT, SA and ZA and SB and Z8 respectively. As described above simultaneous application of set (S) and zero (Z) input signals to a flip-flop has the effect of reversing the state of the flip-flop. Application of only the set (S) signal to the flip-flop has the effect of setting the flip-flop to its 1 state while application of only the zero (Z) signal to the flip-flop has the effect of zeroing the flip-flop to its 0 state.

Returning again to a consideration of FIG. 4 it is seen referring to the short channel, that during the first turn of the short channel the first cell of the short channel and alternate cells thereafter contain phase control marks, each representing a binary 0 while the second cell and consecutively alternate cells thereafter contain so-called dz signals representing the +1 or 1 dz overflow digits arising from the twenty integrator sections.

These dz signals will be hereinafter designated as dzi, dz d2 where the subscript number refers to the number of the integrator section from which the dz signal arises. As shown in FIG. 4, during the first turn of the short channel corresponding to passage of the decode portion of integrator section 7, tin; appears in the second cell of the short channel, the successively thereafter appearing dz signals being dz dZg dz; and then dZgo, dz dz A +1 or 1 value of .a dz overflow digit arising from an integrator section is represented by a l or 0 value respectively of the corresponding dz signal. As will be later explained, at the time that integrator section 7 begins its passage, the new dz signal arising from the immediately preceding integrator section 6, is available in flip-flop B, while as shown in FIG. 4, the old dz signal which must now be replaced, is in the last cell of the short channel (first turn). In the compute operations of the present computer, during this first turn of the short channel, each of the dz signals in the channel is delayed two timing intervals by storage in flip-flop B so that they are precessed or shifted back two cell spaces with respect to their original positions as they are rewritten in the short channel. The new dz signal is inserted in the cell formerly occupied by dz and the old dz signal is not rewritten and is thereby removed from the short channel:

Thus as shown in FIG. 4 during the second turn of the short channel dz (actually dz appears in the second cell of the short channel and dZ7 (actually dz appears in the last cell of the short channel. The dz signals are not processed during the second turn of the aessyes short channel and therefore the appearance of the short channel will be unchanged as it begins its first turn during passage of the decode portion of the succeeding eighth integrator section (not shown). Thus during passage of the eighth integrator section the dzsignal will be appropriately positioned for removal from the short channel (at a time when a new dz will be available from integrator section 7) in the same manner that, during passage of the seventh integrator section, the old dz signal was positioned for removal from the short channel (at a time when a new dz was available from integrator section 6).

As illustrated in FIG. 4, the short channel is synchronized with respect to flip-flop T in such manner that at each appearance of a dz signal flip-flop A output signal T is at a high 1 representing level while at each appearance of a phase control signal in flip-flop A, output signal T is at a low level (and therefore signal T is at a high 1 representing level). Because of the hereinbefore described reversal of signals in transferring from flip-flop A to flip-flop C (and from B to C) each of the dz signals and phase control marks is reversed in value as it is rewritten through flip-flop C into the short channel.

' Thus as illustrated in FIG. 4, during the second turn of the short channel, each phase control mark appearing in fiipflop A has a binary 1 value, while each of the dz overflow signals appearing in flip-flop A are also reversed in value appearing therefore during the next turn of the short channel as complementary signals dz. The described reversal of the phase control marks at each turn of the short channel is one of the features of the present invention. Because of this described operation, the phase control marks always have a 0 value during the decode portion of an integrator section and have a 1 value during the integrate portion of each integrator section. The phase control signals thus unequivocally indicate during computation whether the computer should be in a decode phase of operation or an integrate phase of operation.

For example, a decode phase of operation is indicated at any time T (a timing interval during which signal T is high) by the appearance of a 0 valued phase control mark in flip-flop A, while during any time T a decode phase of operation is indicated by the appearance of a 1 valued phase control mark in flip-flop C. (Since each phase control mark is reversed in value on being transferred from flip-flop A to flip-flop C.) In the same manner as integrate phase of operation is indicated during any time T by the appearance of a 1 valued phase control signal in flip-flop A and at any time T by the appearance of a 0 valued phase control mark in flip-flop V C. This system for identification of decode and integrate portions by means of the alternately reversing values of the phase control marks allows considerable savings in equipment in comparison with that required in the prior art to accomplish the same function.

Referring now to the long channel and eXamining first the decode portion of integrator section 7 shown in FIG. 4, it is seen that the first cell of the decode portion (called the fiducial cell) is reserved for a so-called fiducial mark, this being a 1 valued signal appearing in operation in the first cell of only one of the twenty integrator sections. Excluding the last cell of the decode portion which is always filled with a permanent 0 valued mark, the remaining cells of the decode portion are alternately dx and dy decode cells which are used for storing socalled dx and tdy decode marks, respectively. As shown in FIG. 4 each decode cell is numbered so that it bears the same number as the preceding dz signal. Thus the dy decode cell which is preceded by dz is designated dy decode cell and the following dx decode cell is designated dx decode cell.

A dx decode mark is a 1 valued signal which controls the selection of a corresponding dz signal from the short channel for introduction to the integrator section in? as a dx input. For example a dx decode mark in cell dx has the effect of selecting the dz signal. Normally a dx decode mark will be filled if at all into only one of the dx decode cells.

A dy decode mark is a l valued signal which may be selectively filled into one or a plurality of dy decode cells. Each dy decode mark has the effect of selecting the corresponding dz signal from the short channel, these dz signals being summed to form a dy input to the integrator section. The value of such a sum is called the summation dy (abbreviated Edy). The highest order digit of Edy is carried over to the integrator portion to serve as a dy input thereto. The remaining lower digits of Edy are viewed as comprising a so-called remainder number, the digits of this remainder number being stored in all but the first of those dx decode cells which immediately follow dy decode marks. For example referring to FIG. 4, if dy decode marks had been filled into the 'dy decode cells 5, 4, 2 and 1 then the dx decode cells 4, 2 and 1 would be reserved for the digits of the remainder number. Signals stored in these cells of the operation of the DDA preferably represent the digits of the remainder number (the lower digits of Edy) in what is known as dinary notation. The manner in which the remainder number is represented by bivalued signals in the dinary notation will be described at a later point in this specification.

Referring next to the integrate portion of the integrator section shown in FIG. 4, it is seen that the first cell of the integrate portion is reserved for so-called sign reversal mark, a 1 valued signal which may be selectively filled into this cell. The second cell of the integrate portion always contains a 0 mark and additional 0 marks may be filled into succeeding cells to thereby establish the digit length of the Y and R numbers which are stored in the integrate portion, In the cell following the last of such 0 marks, a so-called exchange mar may be selectively filled. In the cell following the exchange mark there may be filled a so-called integrate mark, a 1 valued signal which is provided to indicate that the remaining cells of the integrate portion will contain signals representing the digits of the Y and R numbers associated with the integrator section. Thus as shown in FIG. 4, the remaining cells of the integrate portion are filled with alternate y signals and r signals designed y y y and r r r r respectively, the y signals representing the associated Y number and r signals representing the associated R number of the integrator section. Insofar as the r signals are concerned, the successive signals r r represent the successive digits in ordinary binary notation of the R number. The signal r for example, is a l or 0 signal representing 1.2- or 0.2 respectively.

In operation of the computer of the present invention, the Y number is not represented, however, in conventional binary notation, but is represented in so-called difference notation, the signals y y, thereby indicating the successive digits of the Y number in this difference notation and the signal y indicating the sign digit of the Y number in this notation. The nature of the difference notation will be explained at a later point in this specification, it being sufficient at this point to state that the Y numbers are initially filled and thereafter generated in this notation.

It will be understood that to place the DDA in operation for solution of a new problem it i necessary to fill into each integrator section y and r signals corresponding to desired initial values of the Y and R numbers for that integrator section and also to fill appropriate signals (dx decode marks, dy decode marks and possibly signals representing initial values of the remainder number of Edy) into the dx and dy decode cells.

Since facilities must be provided for filling signals into the dx and dy decode cells and for filling y and r signals into each integrator section, the same facilities are utilized for filling the remaining cells of each integrator section 17 with appropriate marks, as shown in FIG. 4. In addition phase control marks and initial values of the dz signals must be filled into the cells of the short channel. All of these filling operations may be performed by an operator through utilization of the control switches provided on switch panel 32 shown in FIG. 3.

General Description of Fill Operations The first steps ordinarily performed by an operator in placing the computer into operation for the solution of a new problem, 'is to switch on a power switch 55 thereby supplying electrical power to the computer, and then to place a two-position fill-compute lever switch 56 at its upper or fill position as shown in FIG. 3. Lever switch 56 is always placed in its fill position when filling operations are to be performed and placed at its lower or compute position immediately before compute operations are to be begun.

Next a pushbutton type clear switch 57 is depressed, this having the effect of setting each of the computer flipfiops to its state and also of erasing all signals recorded in the long and short channels, thereby effectively removing from the computer all old information remaining in the computer from previous problems. The pushbutton of clear switch 57 is spring loaded to rise as the operators hand is removed from it, and during this return stroke or up stroke of clear switch 57 the phase control marks and initial 0 values of the dz signals are recorded in the short channel. In addition a single fiducial mark is recorded in the long channel. This recording of the phase control marks and the fiducial mark is called the mark operation. The phase control marks thereafter serve to indicate the boundaries of the decode and integrate portions of each integrator section while the fiducial mark serves as a reference signal which identifies the particular integrator section in which the fiducial mark has been recorded and thereby allows operations to be performed which only pertain to that integrator section.

After a fiducial mark has been inserted in an integrator section through operation of clear switch 57, the remaining cells of that integrator section may be selectively filled with O and 1 signals through utilization of a switch 58 and a switch 59 which are normally spring loaded to an up position. The functions of these switches are dependent upon the position of the fill-compute switch 56, switches 58 and 59 having functions denoted zero and one" respectively when switch 56 is at its fill position and having functions denoted as "start and stop respectively when switch 56 is at its compute position.

When switch 56 is at its fill position as shown in FIG. 3, depression of switch 58 or switch 59 causes a 0 or 1 signal respectively to be filled into the second cell of the integrator section (this being the cell immediately following the fiducial mark). Upon the next operation of one of the lever switches 58 or 59 the previously recorded signal is shifted from the second cell to the third cell of the integrator'section and a new 0 or 1 signal is recorded in the second cell. In the same manner at each successive depression of a lever switch 58 or 59 previously recorded signals are shifted back one cell and a new 0 or 1 signal is recorded in the second cell of the integrator section. Thus in the filling of an integrator section after 79 selective operations of the lever switches 58 or 59 all of the cells of the integrator section will have been filled with desired 0 or 1 signals.

Another spring loaded lever switch 60 is provided, which is sometimes utilized during the filling of an integrator section to accomplish what is called spacing of the signals recorded in an integrator section. Each depression of switch 60 causes all signals (with the exception of the fiducial mark) recorded in the integrator section to shift back one cell. The signal recorded in the last cell is not lost but is brought forward and placed in the second cell. Successive depressions of switch 60 thus 18 causes what might be described as a circular precession or movement of the signals recorded in the channel, each signal moving stepwise backwards towards the last cell of the integrator section and from there being transferred to the second cell from whence it may again be shifted backwards until it reaches its appropriate position, This space operation is commonly utilized when it is necessary to correct errors made in filling an integrator section.

Suppose for example, that after an integrator section has been filled, it was discovered that by error signal y for example, had been recorded as a 1 signal when it should properly have been recorded as a 0 signal. To remedy this error, switch 60 would be successively de pressed to space the recorded signals until the incorrect signal appears in the last cell of the integrator section. Then switch 58 would be depressed once, this having its normal effect of shifting all signals back one cell and of recording a 0 signal in the second cell of the integrator. In this manner the incorrect 1 valued y signal is replaced in the signal sequence by a correct 0 valued signal. Thereafter successive operations of switch 60 are again used to space the recorded signals until the signals have been returned to their proper cells in the integrator section.

It will be understood that switch 60 accomplishes the described space function only when fill-compute switch 56 is at its fill position. Switch 60 as described hereinbelow has a difierent once function when switch 56 is at its compute position.

After one integrator section (that integrator section containing the recorded fiducial mark) has been completely filled in the above-described manner, through operation of a step switch 62, the fiducial mark is shifted or stepped to the succeeding integrator section which may then be filled in the same manner. As illustrated in FIG. 3, switch 62 is a lever type switch normally spring-loaded to an up position. Each depression of switch 62 causes the fiducial mark to be transferred from the first cell of the integrator section in which it is recorded to the first cell of the succeeding integrator section thereby identifying this succeeding integrator section for purposes of filling the remaining cells of the section with desired 1 and 0 signals.

As shown in FIG. 3, immediately above switch 62, there is provided on switch panel 32, a window 63 through which may be seen a disk 64 (indicated in FIG. 3 by dotted lines) which has the numbers 1, 2, 20 printed in order thereon corresponding to the designations of the twenty integrator sections. Step switch 62 is coupled to disk 64 and is effective at each depression thereof for rotating disk 64 so as to display the next successive number. Thus if disk 64 is initially positioned so as to display the number 1 While the first integrator section is being filled, depression of step switch 62 will advance disk 64 to display the number 2 at the same time the fiducial mark is shifted to the second integrator section. In this manner the number appearing at window 63 always identifies the integrator section presently containing the fiducial mark.

After all integrator sections have been filled in the described manner, a computation may be initiated. As a preliminary to initiating computation fill-compute switch 56 is placed at its compute position, this causing switches 58, 59 and 60 to become inactivated for the control of the zero, one and space operations (associated with filling of integrator sections) and to become operable instead for the control of so-called start and once operations respectively (associated with the performance of computation by the DDA). Thereafter, an operator may initiate or start computation by depressing switch 58 and may suspend or stop computation at any time by depressing switch 59. During a complete computation, the long channel may turn hundreds or thousands of times.

During each turn of the long channel, each of the twenty integrator sections contained in the long channel will be processed, each pair of Y and R numbers being advanced in value in accordance with received dz signals. The totality of those computational operations performed during a single turn of the long channel is defined as a unit computation. An extended computation is made up of hundreds or thousands of such unit computations successively performed at very high speeds. If desired however, whenever computation is suspended (as by depressing switch 59), the performance of a single addi tional unit computation may be ordered by depressing switch 69, this performance of a single unit computation being known as the once operation. Each depression of switchfil] causes an additional unit computation to be performed.

The once operation is particularly useful for checking purposes and also for use in introducing abrupt changes in the value of a Y number when it reaches a predetermined value during the course of computation. To accomplish such an abrupt change, computation is stopped at a time when the Y number has slightly less than the predetermined value. Then the once operation may be successively ordered until exactly the predetermined value is attained. Then after raising switch 56 to its fill position, the Y number (and any other numbers if desired) may be altered or rewritten by means of the zero and space operation. Finally, after returning switch 56 to its compute position, computation may be again initiated.

It should be noted that an upper window 66 and a lower window 67 are provided on switch panel 32, through which may be seen upper and lower portions of the viewing face of a cathode raytube 68 (shown in FIG. 3 in dotted outline). During fill operations signals representing the contents of the integrate and decode portions of the integrator section being filled (that section containing thefiducial mark) are displayed in upper window 66 and lower window 67 respectively. During compute operations signals representing the R and Y numbers respectively of the integrate section containing the fiducial mark are displayed in windows 66 and 67. By observing these signals an operator is enabled during fill to monitor the recording of signals into the cells of the long channel and during compute to observe the Y and R numbers stored in the integrator section containing the fiducial mark.

General Description of Compute Operations Facilities are provided in the DDA to supply certain of the dz signals to external output units and also to accept input signals provided by external input units and to utilize them as dz signals. In a particular embodiment of the invention hereinbelow described, the DDA can accept two input signals (designated Input 1 and Input 2 as shown in FIG. 3) at each turn of the long channel or supply two output signals (designated Output and Output as shown in FIG. 3) or can accept one input signal and supply one output signal. When the DDA is supplying two dz signals to external output units (such as graph plotters for example), these dz signals are those arising from the two integrator sections immediately preceding the fiducial mark. When the DDA is accepting two input signals from external inputs (such as curve followers) such input signals are utilized as though they were dz signals arising from the same two integrator sections, these input signals being immediately recorded in the corresponding cells of the short channel so that they can be received by other integrator sections.

When the DDA is supplying one output signal and receiving one input signal, either of the two integrator sections selectively may supply the output dz signal, while the input signal will be utilized as though it were the dz signal arising from the other integrator section. If desired, facilities may readily be provided, as will hereinafter appear, for expanding the operations of the DDA to receive additional input signals and supply additional output signals.

As stated before, after computation is initiated, during each turn of the long channel (during each unit computation) each of the twenty integrator sections contained in the long channel is processed, each pair of Y and R numbers being advanced in value in accordance with dz signals received (via the short channel) from other integrator sections or from a graph follower or other input device. All operations relating to a particular integrator section are performed while that integrator section is traversing beneath read head 45 shown in FIG. 3.

During passage of the decode portion of an integrator section (such as integrator section 7 shown in FIG. 4) a decode or selection operation is performed which is controlled by .the dx and dy decode marks which were filled into the integrator section. During this decode operation one dz signal is selected from the short channel, by means of a corresponding dx decode signal and is stored in flipflop P for introduction to the integrator section as a dx input signal. In addition either one or a plurality of dz signals are selected from the short channel by means of a corresponding dy decode mark or marks. If only a single dy decode mark was filled into the integrator section, then a single corresponding dz signal will be selected from the short channel and will be stored in flip-flop Q for introduction to the integrator section as the dy input signal.

For example, if a dy signal has been filled into the integrator section it will have the eifect of selecting the dZ5 signal for introduction to the integrator section. However if a plurality of dy decode marks are filled into the integrator section, each of them selects a corresponding dz signal, all of the thus selected dz signals are summed in succession to form theEdy number. As each digit is formed, it is stored (in dinary form) in the dx decode cell reserved for it while the carry resultingfrom the formation of that digit is stored in flip-flop Q to be utilized in forming the next digit of Edy. Thus as each successive digit of Edy is formed and stored in its dx decode cell, the corresponding carry digits are successively held in flip-flop Q. At the completion of the process the carry resulting from the formation of the last digit of Edy (thus. corresponding to the highest order digit of Edy) is in Q and serves as the dy input signal. The remaining or lower order digits of the Edy number are stored in the drum and are designated as the Edy remainder number. Thus. upon completion of passage of the decode portion of an integrator section, the dx input signal is available inflipflop P and the dy input signal is available in flip-flop Q.

The 1 and 0 values of the dx signal signify the mathematical values +1 and 1 respectively, while the ITand 0 values of the dy input signal represent the mathematical value +1 x2- or 1 2- Thus the dy input signal has the same weight as the y signal.

During passage of the following integrate portion of the integrator section the presence of a sign reversal mark will have the effect of reversing the state of flipflop P and therefore reversing the sign of the dx signal. If an exchange mark is provided, it will have the effect in further operations of eifectively exchanging the dx signal and the dy signal (thereby permitting the effective dx signal to be formed by summation of a plurality of dz signals). The appearance of the following integrate mark will have the effect of initiating the performance of mathematical operations upon the Y and R numbers stored in the integrator section.

Upon such appearance of the integrate mark (in flipfiop L) a correction signal K is formed in accordance with the dx and dy signals and is stored in flip-flop B. During the ensuing operations, the Y number stored in the integrator section (now called the old Y number) is increased by the value of the dy input signal to form a new Y number whose digits are stored tlll the same cells formerly occupied by the digits of the old Y number. This operation is performed by selectively reversing the signals y y or leaving them unchanged as 21 they are transferred from flip-flop L to flip-flop M in their normal recirculation.

Moreover during the same operations the value of the correction signal K is added to the R number stored in the integrator section (now called the old R number) and in addition the value of the old Y number is added to or subtracted from the old R number in accordance with the +1 or 1 value of the dx signal to thereby form a new R number whose digits are rewritten in the same cells formerly occupied by the digits of the old R numlber. Writing of the new R number is accomplished by selective reversal or non-reversal of the signals r r as they are transferred from flip-flop L to flip-flop M in their normal recirculation through the long channel. The value of the new R number thus formed is defined by the following equation:

The effect of adding K in forming the new R number is to incorporate so-called round-off, trapexoidal and subtraction corrections in the newly formed R number. As a result of the incorporation of these corrections growth of error during the course of computation is greatly decreased.

As each successive r signal of the new R number is formed in flip-flop M, a corresponding carry signal is formed which represents a carry digit arising from the formation of the new r signal, each carry signal as it is formed being placed in fiip-fiop B and being replaced there by the next carry signal as successive r signals are formed. The carry signal arising from the formation of signal r (the last signal of the R number which is stored in the last cell of the integrator section) is the dz signal arising from the integrator section. Since it is placed in the B flip-flop, this dz signal will be available there when the succeeding integrator section begins its traverse and will be as hereinbefore described, transferred from the B flip-flop to the second cell of the short channel during the traverse of the succeeding integrator section;

In this manner the dz signal produced by the integrator section is unloaded via flip-flop B into the short channel where it may be picked up or selected by other integrator sections by means of the dx and dy decode marks filled into the integrator sections.

To briefly summarize: during a traverse of an integrator section one dz signal may be selected from the short channel by the dx decode mark to serve as a dx input signal to the integrator section. One or a plurality of dz signals may he selected from the short channel by the dy decode marks for use in forming the dy input signal. If only one dz signal is selected, it serves as the dy input signal. if a plurality of dz signals are so selected they are summed to form a Edy number whose lower order digits are stored in the long channel for use in modifying later sumrnations while the highest order digit of the Edy number is utilized as the dy input signal.

The dx and dy input signals thus formed are utilized to control the formation of new R and Y numbers. The final carry resulting from the formation of the new R number is the new dz signal arising from this integrator section and is unloaded into the short channel as the succeeding integrator section begins its passage, while shortly thereafter as hereinbefore explained, the old dz signal is erased from the short channel.

Automatic Stop Facilities are provided in the DDA for automatically stopping computation whenever a Y number in any of the integrator sections (exceeds +2 or is less than zero) and therefore cannot be represented in the machine. It will be recognized that after an overflow of a Y number that number will be in error and further computation based upon this erroneous value of the Y number would also be in error. Thus the provision of an automatic stop upon occurrence of overflow prevents the propaga- 22 tion of error into other Y and R numbers. The automatic stop feature may also be deliberately utilized by an operator to stop operation at a predetermined point in the course of a computation, all Y numbers involved in the computation being scaled so that one of the Y numbers will overflow at the predetermined point in the computation.

Idle and Dawdle Conditions It should be understood that when computation is stopped, either automatically or through manual operations of switch 59, the DDA is forced into a phase of operation known as idle in which the signals stored in the long and short channels are merely continuously recirculated without any operations being performed upon the signals. In the idle phase of operation therefore, referring to the long channel each signal arriving in read flip-flop L is transferred unchanged to write flip-flop M. Referring to the short channel, during idle each signal arriving in read flip-flop A is transferred uniformly complemented in value to write flip-flop C. The idle condition exists and is in fact enforced upon the DDA whenever fiip-flop Q is in its 1 state and flip-flop J is simultaneously in its 0 state. The idle condition is therefore indicated by the simultaneous appearance of signals Q and I both at their 1 representing levels (QI) while the absence of the idle condition is indicated whenever signal Q or signal I is high (Q'+J).

The DDA may also enter a temporary idle condition which is called dawdle. The dawdle condition can only exist when fill-compute switch 56 is at its fill position and then is enforced upon the DDA whenever flipflops Q and J are simultaneously in their 1 state as indicated by the simultaneous appearance of signals Q and I at their high levels (Q-]).

The output signals I and I produced by flip-flop I are utilized very extensively in the operation of the DDA, primarily for identifying certain portions of each integrator section. It is therefore desirable for purposes of explaining the functioning of the DDA to provide some preliminary information concerning operation of the I flip-flop. It will be shown that during each passage of an integrator section flip-flop I is always sent to its 0 state immediately after passage of the second cell of the decode portion of the integrator section. If fill-compute switch 56 is at its fill position or if the DDA is in an idle condition, flip-flop I will be returned to its 1 state immediately after passage of the first cell of the integrator portion. However if this condition does not exist (if switch 56 is at its compute position and it is not idle) then flip-flop I will be returned to its 1 state only upon the appearance of the integrate mark in flip-flop M. For purposes of illustration a waveform of output signal I is shown in FIG. 5 as it would appear during computation for passage of integrator section 7 shown in FlG. 4 (assuming that an integrate mark has been filled into the section). A dotted line 70 indicates the variation in this waveform which would be present when the DDA is in its idle condition or switch '56 is at its fill position.

Detailed Description of Structure and Operation Virtually all of the operations of the DDA have now been described with varying particularly in the general description of operation provided in the preceding portions of this specification. All of the above-described operations of the DDA will now be reviewed in great detail both to further clarify the nature of the operations performed and to fully disclose the electrical circuits and apparatus which are utilized in a preferred embodiment of the invention to mechanize these operations. Basically in the preferred embodiment of the DDA all operational processes are carried on by successive changes in the states of the computer flip-flops.

At the end of each timing interval (as demarked by the appearance of a clock pulse Cl) each computer flipflop is either se (sent to its 1 state by application of input signals to its set (S) input conductor) or zeroed (sent to its state by application of input signals to its zero (Z) input conductor) or is triggered (reversed in state by simultaneous application of input signals to both its S and Z conductors). Flip-flops A and L are set or zeroed in accordance with the binary 1 or 0 value of the magnetic signals, then traversing past read heads 40 and 45 respectively. Flip-flop T is regularly triggered by application of clock pulses CI to both its ST and ZT input conductors. The remaining flip-flops B, C, Q, M, J, I and P are set," zeroed or triggered" in accordance with the states of other computer flip-flops and positions of the front panel switches during the preceding timing interval.

To accomplish the described operations, during each timing interval all of the output signals produced by the computer flip-flops are applied to gating matrix 31. These output signals as hereinbefore described represent the states of the flip-flops during the timing interval.

In addition, switch signals arising from the switching provided on panel 32 are applied to gating matrix 31, and also input signals arising from external sources (such as curve followers for example) may be applied to gating matrix 31. Gating matrix 31 is responsive to the signals applied during a timing interval and to the application of a clock pulse CI for selectively applying electrical pulses to thefset and zero input terminals of each of the flip-flops. For example, at the end of each timing interval, gating matrix 31 may apply an SC input pulse to the SC input conductor of flip-flop C or a 20 input pulse to the ZC input conductor of flip-flop C or may apply input pulses to both input conductors simultaneously.

It will be shown that gating matrix 31 comprises a plurality of gating networks, each gating network receiving some of the signals applied to the gating matrix and combining these signals to form one of the output signals produced by the gating matrix. Thus gating matrix 31 includes a gating network for producing the SC signal, another gating network for producing the ZC signal and so forth, there being one gating network respectively for each of the output signals produced by the gating matrix. Each of the gating networks will ordinarily include a plurality of logical and gates and or gates arranged to combine applied signals in accordance with an associated Boolean logical equation to produce a desired resultant output signal. As is well known in the art, the Boolean logical equation associated with a gating network fully defines the output signal produced by the network in terms of the input signals received by the network and in addition supplies a complete description of the structure of the gating network.

For example, referring now to FIG. 6a, there are illustrated two gating networks 101 and 102 which form output signals SC and ZC respectively, these signals, as illustrated in both FIGS. 3 and 6a, being applied to flipfiop C to respectively set and zero the flip-flop. In reference to their functions, gating network 101 will be referred to as the Set C Gating Network and gating network 102 will he sometimes referred to as the Zero C Gating Network. Other gating networks will similarly be designated in terms of the output signals they produce.

As shown in FIG. 6a, set C gating network 101 includes a conventional diode and gate 83 which receives signal A and a signal Klup (a high level signal generated by clear switch 57 in its up position) and combines these signals to produce a bilevel output signal Alg which has a high level only when both signals A and Q are at their high levels. The expression A'Kl thus .symbolizes the performance of the logical and" operation. The signals A'Kl is applied to one input of a second and gate 84, symbolically represented as a semicircle containing a dot which also receives clock pulse in such operations.

signal Cl, gate 84 being effective for producing an output signal C1[A' I only when signal Alil is at a high level and the clock pulse Cl appears. As shown in FIG. 6a this output pulse signal is the output pulse SC.

A Boolean logical equation which defines output signal SC in terms of the received signals -A, K1 and Cl may be formed by setting SC equal to itsq uivalent form Cl [A' l 1 u 6 Equation 1 states in a very concise form that an output pulse SC will be produced only when signals A and K1, are both at their high levels and a clock pulse signal Cl appears.

As a further illustration consider the zero C gating network 102 shown in FIG. 6a. Gating network 102 is seen to include a conventional diode or gate 85 which receives signals Q and J and combines these signals to produce a bilevel signal (Q+J) which has a high level only when signal Q or signal I is at a high level. In the expression (Q+J) the symbol indicates the performance of the logical or operation as shown in FIG. 6a. Signal '(Q'+]) is applied to one input of an and gate 86 which receives at its other inputs signals T, B and a signal Com. Gate 86 combines these signals to produce an output signal TBCom (Q'+ J) which has a high level only when all the input signals to gate 86 are at their high levels.

Another and gate 87 is provided which receives signal A and a signal Com and combines these signals to produce a resultant output signal Am. It will be shown hereinbelow that signals Com and Com are complementary bilevel signals derived from fill-compute switch 56, signal Com having a high level when switch 56 is at its fill position and signal Com having a high level when switch 56 is at its compute position. (In the following specification, designations of signals arising from switches will be invariably underlined so as to clearly distinguish switch derived signals from other signals.)

Continuing with the description of gating network 102 shown in FIG. 6a, it is seen that an and gate 88 is provided for combining signals A and T to produce a resultant signal AT and another and gate 89 is provided for combining signals A, Q and J to produce a resultant signal AQJ'. The signals produced by and gates 86, 87, 88 and 89 respectively, are applied to an or gate 90, symbolically designated as a semicircle with a contained therein, gate 90 combining these applied signals to produce a resultant output This signal produced by or gate 90 is applied to one input of an and gate 91 which also receives at another input clock pulse Cl, gate 91 combining these signals to form the output signal ZC where the signal ZC is defined by the Boolean equation:

In logical Equation 2 each sign indicates the performance of a logical or operation of the signals combined thereby and the absence of a'(+) sign indicates the performance of a logical and operation upon the signals combined thereby.

It will be apparent to those skilled in the art that logical Equations 1 and 2 completely specify the specific mechanizations of gating networks 101 and 102 shown in FIG. 6a, that is, the equations specify both the number of logical and and or operations to be performed by the networks as well as the factors and terms involved For example, the bracket in Equation 2 specifies an overall logical and operation involving two factors, namely, Cl and the quantity within the bracket. This operation is performed by an and gate, gate 91, which includes two inputs, one for each factor, and two diode rectifiers, one for each input.

Similarly the quantity within the bracket represents a logical or operation involving four terms, namely, TBCom(Q+J) Q T. and Aggy. This operation is performed by an or gate, gate 90, which includes four inputs, one for each term, and four diode rectifiers, one for each input. The four terms specified in the logical or operation are, in turn, specified by further logical and operations. More particularly, term AQJ' specifies a logical and operation performed by three-terminal and gate 89; and terms AT and AC m' logical and operations performed by twoterminal and gates 88 and 87, respectively. Term TBC m 1(Q'+J) specifies a logical and operation performed by four-terminal and gate 86 which, in turn, has one terminal connected to the output terminal of twoterminal or gate 85 as specified by the factor (Q'+J).

It is thus seen that the logical equations specify exactly the mechanizations of the associated gating networks, including the number of gates, the number of input terminals for the gates, and the interconnections of the gates. In addition, it is apparent to those skilled in the art that the equations, such as Equations 1 and 2 may be varied in accordance with the well-known rules of Boolean algebra to yield equivalent mechanizations having different numbers of gates, terminals and interconnections. For example, the quantity within the bracket of Equation 2 may be factored to yield the following:

ZC=C1[TB Q%(Q'+J) +A (QJ'+T'+C1 In accordance with the rules set forth above, this equation would be mechanized a two-terminal and gate, identical to gate 91 for the and operation between Cl and the bracketed factor; a two-terminal or gate and a four-terminal and gate, identical to gates 85 and 86, respectively, for the term TBQ (Q'+ J a twoterminal or gate, similar to gate 90, for the or operation between the term TB9Q m (Q'+J and the term A (Q J+T'+ m) a two-terminal and gate for the and operation between factor A and factor a three-terminal or gate for the or operation between terms QJ, T, and Q2 and a two-terminal and gate for the once operation between factors Q and I.

It is, therefore, apparent that logical equations com pletely specify gating mechanizations. In addition techniques for rnechanizing Boolean equations are well known in the art. See, for example, an article entitled An Algebraic Theory for Use in Digital Computer Design, by E. C. Nelson, found in the Transactions of the IRE, September 1954 issue, pages 12 through 21. Accordingly, for purposes of clarity and more complete understanding of the present invention, the remainder of this specification, except for the description of FIG. 6b, will be devoted to a non-rigorous derivation of logical equations which satisfy the requirements of the general terms and conditions of operation set forth above in the general description.

The equations thus derived will be mechanized by gating matrix 31 which, as illustrated in FIG. 3, produces twenty-two output signals from twenty-two correspond ing gating networks, as specified by the associated equations. For purposes of handy reference, all of the equations to be derived are set forth below in Table 1. In addition all of the terms of the equations are numbered 26 in the order in which these terms are developed in the following portions of the specification.

+ ComTCl'vlJLB' ComITCLMP' 34 43 

